1. Field of the Invention
The present invention relates to a wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the contacting of any wafer. More particularly, the invention also relates to method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system.
In order to reduce the extent of any reliability failure rate which may be encountered during the early life of integrated circuits, semiconductor VLSI/ULSI products are usually subjected to burn-in or temperature/voltage screens that are designed to screen out any present or potential failures due to manufacturing defects, which otherwise may occur at an early time during field operations. The burn-in is normally carried out at the packaged level of individual product chips, whereby each product wafer is initially diced out and each product chip is mounted in a package which could be constituted of plastic or ceramic. The individual packaged product chips are then mounted on custom designed circuit boards, and these boards are thereafter placed in burn-in chambers where temperature are readily controlled to up to 140 C or even higher. These circuit boards are custom designed for each type of product or product family (e.g. SRAM, DRAM, LOGIC . . . ) where the power supply pin or pins on each product chip package is or are energized through the power supply buses provided on the printed circuit board or card. Moreover, the data and address pins or the product chips are connected through special buses to externally supplied data and address lines.
Consequently, through the application of this package level stress system, many product packaged chips are placed under the burn-in process for a period that can readily range from about 2 hours up to 24 hours, or even lengthier periods of time. During the burn-in process, the integrated product chips are dynamically stressed under elevated voltage and temperature conditions. Across the extent of the industry, it has been recognized, for some users, that the presently employed and generally conventional burn-in procedure is quite expensive and resultingly contributes significantly to the overall cost of the product, however, at the same time it is deemed to be an important procedure which semiconductor manufactures must necessarily implement in order to sell product chips possessing a good reliability, but which means having to sell them for more money. The high cost of burn-in stems from the need for custom designed stress cards for each product, product family, package or package type, and the need for furnishing high temperature stress chambers which are custom built with the provision of stressors able to exercise each product dynamically and in a manner which closely controls the magnitude, and timing of the various supply pins, data buses and address signals. A considerable amount of labor and expenditure of money is involved in the process of implementing the designing, building, and maintaining those stressors and stress boards, as well as conducing of the burn-in procedure. There is also encountered the problem of low burn-in efficiency and burn-in escapes, represented by those particular chips which are not imparted a proper or adequate burn-in on a given stressor system, for example, due to broken pins, faulty connections, and inadequate handling of the packaged chips.
Another important procedure which semiconductor manufacturers carry out in order to improve upon encountered premature or early failure rate is a voltage screen, which involves applying a high voltage at a moderate temperature for a period of only a few seconds or the like. The voltage can be applied statically or in a dynamic manner.
These screens are usually implemented at wafer level, by means of a probe contacting one wafer at a time. For the screens, the temperature cannot be as high as desired, because of possible probe contact problems at high temperature. The problems with the present system for voltage screens are; firstly the cost involved with probe contacting only one chip at a time, and secondly, the necessary temperature limitations.
In addition to the foregoing difficulties encountered in the technology, the performance of semiconductor technology reliability evaluations for the various reliability failure mechanisms, during technology development represents another source of excessively high cost and time factors with regard to the overall test program budget. Normally, the reliability failure mechanisms which are usually evaluated include: electromigration, dielectric reliability, hot carriers, bias temperatures stability, vias and contacts. These reliability failure mechanisms are normally evaluated in an individual manner, employing specially designed test structures, test and stress conditions for each mechanism. Many, if not all, of the reliability failure mechanisms are evaluated at wafer level, by probe by singly contacting each chip one-at-a-time in order to perform the required stress procedure. It is also important to note, that for every failure mechanism, many different test structures are specifically designed to carry out only a specific purpose, such as a specific type of device layout, certain specific design dimensions, or to perform a predetermined design function. The individual test structures (or test macros) are usually closely packed inside the test chip, with sufficiently small probe pad sizes, such that normally only one test structure, (or macro) is probed and stressed an any given instance of time. Consequently, stressing all of the required test structures for all the reliability failure mechanisms is a very time consuming and intensive process, and represents a substantial portion of the overall development costs. Each evaluation of a specific reliability mechanism, requires certain stress conditions, such as a constant current at elevated temperatures for electromigration and dielectric reliability, a constant voltage at low or elevated temperatures for hot carriers, a bias temperature stability, and dielectric reliability. Thus, were it possible to be able to supply certain current or voltage conditions on each test structure, it would become possible to evaluate many mechanisms simultaneously, since there could be employed a common temperature for conducting the stress for those mechanisms.
In manufacturing, routine in-line reliability monitoring is an absolute requirement in order to protect the quality and reliability of shipped products. This monitoring is implemented for many, if not for all of the key reliability failure mechanisms. The monitoring for reliability failure mechanisms has to be carried out such that the stress time involved in the evaluation is sufficiently short, so that the routine testing for adequate numbers of samples is economical in its application. The testing on each wafer is done for a certain number of chips, by the probe contacting each chip one at-a-time. For high volume manufacturing production, the number of wafers monitored for reliability is very high, such that the total time required to perform the stress testing on all chips becomes quite significant. However, in the event that the stress testing can be performed on many or all chips simultaneously, that would represent a significant saving in the overall time required for that purpose.
2. Discussion of the Prior Art
Although a considerable amount of investigative work has been carried out in the technology in connection with wafer level burn-in, particularly for all chips simultaneously, the current state-of-the-technology still does not clearly provide for a unique and advantageously implementable wafer level system analogous to that disclosed by the present invention.
In the present state-of-the-technology, there are many patents which direct themselves to for wafer level burn-in of all chips simultaneously; however they are all based on systems or structures which enable making common connections to all chips on the wafer, and those common connections are accessible through pads to external exercises for burn-in procedures. All of the concepts used for this prior art require complicated systems with difficult requirements of tolerances, thermal properties and matching properties. Also, these prior art publications would not be satisfactory for very high frequency chip technology because of the need for additional off chip contacting fixtures.
Among the foregoing patents which are considered to be of general interest, but which are not applicable to the inventive concept as set forth and claimed herein are Leas, et al. U.S. Pat. No. 5,600,257; Charlton, et al. U.S. Pat. No. 5,528,159; Anschel, et al. U.S. Pat. No. 5,420,520; Campbell, et al. U.S. Pat. No. 5,399,101; Smith, et al. U.S. Pat. No. 5,047,711; Kreiger, et al. U.S. Pat. No. 5,210,485; Devereaux, et al. U.S. Pat. No. 5,279,975; Chiu U.S. Pat. No. 5,307,010; Rostoker, et al., U.S. Pat. No. 5,389,556; Green, et al. U.S. Pat. No. 5,424,651; King, et al. U.S. Pat. No. 5,440,241; Rostoker, et al. U.S. Pat. No. 5,489,538; and Atkins, et al. U.S. Pat. No. 5,570,032.
There are also patents and other publications in evidence which disclose methods and systems that allow contactless testing of all chips on a wafer simultaneously without having to probe each chip at a time. It should be noted, however, that those prior art publications are primarily for initial device characterization and measurements, and not for burn-in, voltage screen, or reliability evaluations of failure mechanisms.
Thus, Verkuil U.S. Pat. No. 5,216,362, which is commonly assigned to the present assignee, discloses a system intended to measure epitaxial dopant profile in semiconductor wafers in a non-contacting procedure. This is achieved by forming a temporary P-N junction in the surface of the semiconductor wafer using Corona discharge.
Verkuil et al. U.S. Pat. No. 4,812,756 is concerned with disclosures of a contactless technique which allowed for making time retention and epi-doping concentration measurements.
In Verkuil U.S. Pat. No. 5,485,091 a contactless system is employed for measuring the thickness of very thin oxide layers on a silicon substrate. This is effected by a Corona discharge source which repetitively deposits a calibrated fixed charge density on the surface of the oxide, and the resultant change in oxide surface potential for each charge deposition is measured. In Verkuil U.S. Pat. No. 5,442,297), a contactless system is described which measures the sheet resistance of a desired layer of a first conductivity type formed upon a substrate of an opposite conductivity type. The apparatus comprises a junction capacitance establishing means, a point location alternating current AC photovoltage, an attenuation and phase shift monitoring means for monitoring the laterally propagated AC photovoltage, and a sheet resistance signal generating means responsive to the junction capacitance establishing means, the AC photovoltage generating means, and the attenuation and phase shift monitoring means for generating an output signal indicative of a sheet resistance.
Also set forth in a copending U.S. patent application Ser. No. 09/250,880, W. A. Abadeer, et al. entitled “Apparatus and Method for Non-Contact Stress evaluation of Wafer Gate Dielectric Reliability”, is a wafer contactless system for gate dielectric reliability stress evaluation. In the system described therein, exposure of wafer to hydrogen plasma was shown to induce degradation in the thin gate dielectric, and this degradation was correlated and related to the systematic process of thin gate dielectric degradation, leading to breakdown under conventional voltage/temperature stressing with probe contacting.
In this prior art, wherein wafers are exposed to the hydrogen plasma and the change in interface state density due to hydrogen exposure is measured. That system, however, cannot be used for fully processed and integrated wafers with metal levels because the lateral transport of atomic hydrogen in metal-oxide-semiconductor capacitors with aluminum or polysilicon gates is extremely limited. This means that the evaluation for gate dielectric reliability need to be done on gate free samples after the deposition of the thin gate dielectric, without depositing an polysilicon or metal levels. Also the technique can not be used for evaluation of other reliability failure mechanisms such as hot carriers, electromigration and bias temperature stability. It also cannot be used for burn-in of product chips.